In many systems, in particular in radio communications, there is a need to process a signal non-linearly. The objective is typically that the signal should stay within certain constant or signal-dependent boundaries. It is often desirable that the signal also is kept within a certain bandwidth, so that it does not spill over into adjacent channels or exceeds spectral emission limits.
High-performance non-linear processing often requires a number of processing stages, which results in high hardware use and high power consumption. Often, high sample rates are also needed, which further increases the requirements in terms of power and hardware. Many operations per sample at high sample rate require a lot of power. Furthermore, high sample rate also requires large number of gates, in turn leading to large chip area, i.e. high hardware consumption. Some prior art systems recognise that this may be a problem in certain applications, and suggestions leading to reduced number of processing stages and/or reduced required sample rate without significantly reducing the signal quality have been presented, which aim to bring down the power consumption to more manageable levels.